1. Field of the Invention
The present invention pertains to data writing and data reading in FIFO buffer memories and more particularly to data writing in fallthru conditions where the read pointer and the write pointer are in the same row of the memory.
2. Related Prior Art
In present technology, data is written and read in FIFO memories at ever increasing speed. In a FIFOs memory, data is written one cell at a time while data is read onto the bitlines a complete row at a time. A condition called fallthru occurs when the read pointer and the write pointer are in the same row, with the write pointer being ahead of the read pointer. In this situation, when the write pointer is not finished with the row and the read pointer is enabled, the entire row of data is read onto the bitlines. The data at the end of the row and ahead of the write pointer which was read onto the bitline will be incorrect or unreliable.
Prior art has provided a solution to this problem by shorting the read bitline and the write bitline together in the fallthru case, where the read pointer and the write pointer are in the same row with the FIFO almost empty (the write pointer is ahead of the read pointer in the row).
In a typical dual-port memory cell for a first-in first-out memory circuit, the cell is provided with a pair of write bitlines through which data in the form of a 1 or a 0, may be entered into the cell. The cell is likewise connected to a pair of read bitlines through which one can read the contents of the cell.
In such a first-in first-out memory circuit, data entered at the inputs appears at the outputs in the same order, the data "falling through" to the output queue with a small delay. While such typical design is rapid and effective in use, it is generally desirable to reduce the overall delay time for providing to the output queue the data written into the memory.
In one type of system in the prior art, rapid access to the data on memory cell write bitlines by the read bitlines of the memory cell is allowed in the case where the memory cell is being accessed by appropriate row and column pointers by shorting read and write bitlines.
This type of prior art circuit has one or more write bitlines connected with the memory cell for communicating data to the cell, one or more read bitlines connected with the memory cell for communicating data from the cell, and a logic circuit for connecting the write bitline with the read bitline independent of the cell so that data carried by the write bitline can be communicated to the read bitlines independent of the memory cell.
FIG. 1 illustrates a prior art circuit that attempts to solve the fallthru problem that can be found in U.S. Pat. No. 4,802,122. Referring to the drawing, a typical memory cell 10 is illustrated in the dotted box. This memory cell is representative of the more than one thousand that are contained in a 1K memory array.
The memory cell 10 includes a voltage supply terminal V.sub.cc, a resistor 14 connected to the voltage supply, V.sub.cc, and an N-channel MOS transistor 16 having its drain connected to the resistor 14. In parallel with the resistor 14 and transistor 16 are another resistor 18 connected to the voltage supply terminal V.sub.cc, and another N-channel MOS transistor 20 having its drain connected to the resistor 18. The sources of the transistors 16 and 20 are connected to ground terminals 22. The drain of transistor 16 is connected to the gate of transistor 20 and the drain of transistor 20 is connected to the gate of transistor 16.
N-channel MOS transistors 24, 26 have their sources connected to the drain of the transistor 16, while N-channel MOS transistors 28, 30 have their sources connected to the drain of the transistor 20. The drain of the transistor 24 connects to the external write bitline 32, while the drain of the transistor 26 connects to the external read bitline 34. Similarly, the drain of the transistor 28 connects to another external write bitline 36 while the drain of the transistor 30 connects to another external read bitline 38. The gates of the transistors 24 and 28 connect to the external write word line 40, while the gates of the transistors 26 and 30 connect to the external read word line 42. The logic states of the write word line 40 and read word line 42 are input into an AND gate 44. The output signal of the AND gate 44 is input to the gates of N-channel MOS transistors 50 and 52. Transistor 50 provides connection between the write bitline 32 and read bitline 34 when transistor 50 is on. Transistor 52 provides connection between the write bitline 36 and read bitline 38 when transistor 52 is on.
Data is communicated from a data input line through a buffer (not shown) to write bitline 32 and through an inverter (not shown) to the write bitline 36. Thus, whatever the state of the input signal, the write bitline 32 and write bitline 36 will carry opposite values (D and D). Assuming, for example, that a 1 is provided as the input signal on line 34 to be written into the memory cell 10, the write bitline 32 will carry a high signal and the write bitline 36 will carry a low signal. The write row line 40 is activated to turn transistors 24 and 28 on, so that the drain of transistor 16 goes high, turning the gate of transistor 20 on and bringing the drain of transistor 20 and the gate of transistor 16 low, so that transistor 16 is off and transistor 20 is on.
Assuming that such data is needed to be read from the memory cell 10, the read row line 42 is activated, turning on transistors 26 and 30. The cell's data is placed on the read bitlines 34 and 38 and the data applied to a sense amplifier, communicating with a line from which the ultimate output is taken.
In this circuit, upon the write row line 40 and read row line 42 being simultaneously addressed, the signal from the AND gate 44 is high. The transistors 50 and 52 are turned on, providing direct communication between the write bitline 32 and read bitline 34, and also between the write bitline 36 and read bitline 38. Thus, in this situation, data is written into the memory cell 10 as was previously described. However, because of the direct communication between the lines as described above, the data being supplied by the write bitlines 32 and 36 can be read faster than in the prior art description, since the data is transferred directly from the write bitlines 32 and 36 through transistors 50 and 52 to the read bitlines 34 and 38, respectively.
An additional prior art method is the TBus Shorter method which can be used on a typical dual-port memory cell, having write and read column select circuitry. In this method the write bitlines are shorted to tbus and tbusb (the differential inputs of the sense amplifier) in order to reduce the fallthru delay.
The tbus shorter method that was previously used, placed constraints on the timing of the column select circuitry and the tbus shorter signal. When a write occurs and the write bitlines are column selected the data is written onto the write bitlines by the data input driver. When the write wordline is turned on, the memory cell is written. Now the Write operation must also flip the read bitlines through the small pass gates of the dual port memory cell. If the Write bitline driver and the write wordline turn off prior to the read bitlines being flipped then there is a possibility that the read bitlines may over-write the memory with wrong data, resulting in a functional failure, or a downbinning due to required longer cycle times.